Random access memory devices that are widely used to store data in a computer are frequently classified as DRAMs (Dynamic RAMs) or SRAMs (Static RAMs). A DRAM includes a plurality of memory cells each consisting of a capacitor and a transistor, which store a single bit of data. Generally, a DRAM includes a plurality of banks of memory cells that are arranged in a row-column format. A bank may be composed of one or more DRAM blocks sharing timing control signals and memory cells arranged in a bank share address and control signal lines as well as data buses. Each bank acting as an independent chip has a row decoder and a column decoder and can operate independently as a DRAM.
Data, which has a high level (“1”) or a low level (“0”) according to the level of charges accumulated on a cell capacitor, is stored in a DRAM. However, since the charges accumulated on the capacitor are gradually discharged, determining the logic level of the data after a predetermined time may become difficult. Therefore, it is necessary to periodically perform refresh operations for amplifying and maintaining the stored data.
Here, a time measured from when the charges accumulated on the capacitor begins to be discharged to when the logic level (“0” or “1”) of the data cannot be reliably determined is called a refresh period. The number to cycles taken to refresh all rows of a DRAM is called a refresh cycle. Also, a refresh interval is a time interval between refresh cycles when refresh operations are performed per a predetermined time.
The plurality of banks have the same configuration. In each bank, refreshing is performed row-by-row. Since each bank operates independently, while a read operation is performed in a bank, a write or refresh operation can be performed in another bank. FIG. 1 shows a conventional memory device 100 using a conventional refresh method. Referring to FIG. 1, the memory device 100 includes a refresh controller 110, a refresh-access arbitration unit 130, a cache 150 including a cache access unit CSA and a cache memory CSM, and a plurality of banks 170-0 through 170-(N-1) including bank access units BKA-0 through BKA-(N-1) and bank memories BKM-1 through BKM-(N-1), respectively.
The refresh controller 110 transmits a refresh request signal RQS for refreshing the plurality of banks 170-1 through 170-(N-1). The refresh-access arbitration unit 130 arbitrates refresh and access operations for the plurality of banks 170-0 through 170-(N-1). That is, the refresh-access arbitration unit 130 allows the plurality of banks 170-1 through 170-(N-1) to be refreshed if a refresh request is issued, and allows a specific bank to be accessed through a cache if an external access to the specific bank is requested. However, if an external access (a write access for writing data in a memory and a read access for reading data from a memory) and a refresh operation for a specific memory bank are simultaneously requested, the external access is limited, which deteriorates the performances of an entire system.